DESIGN AND IMPLEMENTATION OF ENERGY-EFFICIENT CMOS VOLTAGE LEVEL SHIFTERS FOR MULTI-CORE APPLICATIONS

Abstract

This article proposes three single supply energy-efficient low-power voltage level shifters that are suitable for input/output (I/O) and chip core interfaces in multi-core applications. The circuits are implemented in 180 nm technology and simulated using Cadence Spectre with two different supply voltages; the simulated results show better improvement in energy and average power of 2, static power of 41.3, and delay of 55.8 @ 1.8 V than the existing level shifters. These technological advancements in the field of low power digital CMOS circuits. The voltage conversion range is 580 mV to 3.3 V, or threshold voltage to I/O voltage level. The post- layout simulation confirms resilience of voltage level conversion of the suggested circuits. Because of a major enhancement in latency, static power, energy and conversion range the suggested circuits are ideal for low-energy applications and lowpower chip core-I/O interfacings.