POWER-EFFICIENT NOR GATE USING FINFET TECHNOLOGY

Abstract

With the continuous downscaling of CMOS technology into the sub-22nm regime, conventional planar transistors suffer from increased leakage currents, short-channel effects, and degraded power efficiency. Fin Field-Effect Transistor (FinFET) technology offers a compelling solution through its three-dimensional multigate structure, providing superior electrostatic control over the channel region. This paper presents a Power-Optimized FinFET NOR Gate incorporating Energy Recovery Switching (ERS). The proposed circuit employs double-gate 16nm FinFET devices with an optimized pull-up (PMOS series) and pull-down (NMOS parallel) network, achieving significant reductions in both static and dynamic power dissipation. Energy recovery switching minimizes charge dissipation during output transitions by partially recycling energy stored in the load capacitance. Simulation results at 16nm demonstrate an average power reduction of 50.8%, propagation delay improvement of 39.1%, and power-delay product (PDP) improvement of 70.1% compared to conventional FinFET NOR gates. The proposed design is highly suitable for IoT devices, wearable electronics, mobile processors, and embedded systems. Keywords: FinFET Technology, NOR Gate, Energy Recovery Switching, Low-Power VLSI, Power-Delay Product, Short-Channel Effects, Leakage Current, Nanoscale Design, SPICE Simulation, Digital Logic.