A Runtime-Configurable Exact/Approximate 16-bit Adder for Dynamic Accuracy-Power Tradeoffs

Abstract

Approximate adders typically fix their accuracy-power operating point at design time, forcing designers to choose a single tradeoff for the lifetime of the circuit even though workload accuracy requirements often vary at runtime. This paper presents a runtime-configurable 16-bit adder built from four cascaded 4-bit segment adders, in which a single control bit, `mode_approx`, selects between two operating modes using identical hardware: when `segment carries are chained normally, reproducing an exact ripple-carry result; when `mode_approx = 1`, each segment's carry-in is forced to zero, allowing all four segments to add in parallel at the cost of a bounded intersegment carry-propagation error. The design is compared against a conventional exact 16-bit ripple-carry adder, both captured in synthesizable Verilog, functionally verified with Icarus Verilog, and synthesized/implemented on a Xilinx Artix-7 FPGA (xc7a100tcsg324-1, Vivado 2019.2). Postimplementation results show the configurable adder matches the plain ripple adder's 16-LUT footprint while reducing critical-path delay from 8.623 ns to 7.599 ns (11.9% faster) and improving throughput from 115.97 to 131.6 MOps/s, even under the conservative worst-case timing view that covers both operating modes. Exhaustive and random-vector characterization of the approximate mode confirms an 84.6% mismatch rate against the exact result with a maximum absolute error of 4368 — exactly matching the theoretical worst case of  from the three inter-segment carry chains — validating that the observed error behavior is a direct, predictable consequence of the forced carry-in design rather than an artifact of implementation. These results demonstrate that a single reconfigurable adder can deliver both an exact reference mode and a materially faster approximate mode from one synthesized netlist, without any area penalty relative to a fixed-precision baseline. Keywords: configurable approximate adder, runtime accuracy-power tradeoff, segmented adder, approximate computing, low-power VLSI, FPGA synthesis, carry propagation error