Error-Resilient Approximate Full-Adder Architectures for Low-Power Arithmetic: A Comparative Error and Power Analysis
DOI:
https://doi.org/10.62643/Abstract
Approximate arithmetic circuits trade a controlled loss of numerical accuracy for reductions in area, delay, and power, making them attractive building blocks for error-tolerant workloads such as image processing, machine learning inference, and multimedia signal chains. This paper presents a comparative study of four approximate full-adder (AFA) variants against an exact CMOS full adder, each variant formed by deliberately omitting one term of the exact sum/carry Boolean equations. A unified error-analyzer architecture is proposed that instantiates all five adders in parallel, drives them from identical primary inputs, and flags per-vector sum and carry mismatches against the exact reference in a single pass, enabling exhaustive characterization over all eight input combinations without repeated re-synthesis. The design is captured in synthesizable Verilog, functionally verified with Icarus Verilog, and synthesized and implemented on a Xilinx Artix-7 (xc7a100tcsg324-1) device using Vivado 2019.2. Post-implementation results show the exact adder occupies 2 LUTs at 2.095 ns delay and 0.084 W power, while the five-adder analyzer occupies 11 LUTs at identical delay and power, since the analyzer's critical path is bounded by the same two-level adder logic. Error characterization shows total bit-error counts of 1, 1, 2, and 6 (out of 8 input patterns) for AFA Type 1 through Type 4 respectively, exposing a clear accuracy-complexity ordering among the variants that is not visible from area or delay alone. The results demonstrate that per-cell approximate adder savings must be evaluated independently of the parallel-comparison analyzer overhead, and provide a reusable methodology for rapid, exhaustive error profiling of approximate arithmetic cells. Keywords: approximate computing, approximate full adder, error-tolerant arithmetic, low-power VLSI, FPGA synthesis, error analyzer, CMOS adder design
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