PROGRESSIVE FLEXIBLE DSP ARCHITECTURES FOR HIGH PERFORMANCE SIGNAL PROCESSING ON FPGAS

Abstract

The rapid growth of communication systems, multimedia applications, biomedical devices, and embedded platforms has significantly increased the demand for high-performance Digital Signal Processing (DSP) processors with low hardware complexity and energy consumption. Conventional DSP architectures often experience high silicon area, increased processing delay, and excessive power consumption due to inefficient arithmetic units and dedicated hardware implementations. To address these challenges, this research presents a progressive VLSI design methodology for developing optimized DSP architectures with enhanced computational efficiency and hardware utilization. Initially, a Low-Cost Radix-4 Reconfigurable Finite Impulse Response (LCR4-RFIR) filter architecture is developed using Dynamic Reconfigurable Partial Product Generators (DRPPG) and Radix-4 multiplication to minimize hardware resource utilization and computational complexity. Subsequently, a Gaussian Window driven Least-Squares Linear Phase FIR (GW-LS-LP-FIR) architecture is proposed to improve filtering accuracy, reduce critical path delay, and lower power consumption through optimized coefficient generation, symmetry-based multiplier reduction, and pipelined processing. Building upon these improvements, a Flexible-DSP core is designed to dynamically select FIR Filter, FFT, or Convolution Accelerator operations using a shared reconfigurable hardware architecture, thereby enabling efficient execution of multiple DSP kernels within a single VLSI platform. The proposed architectures are designed, simulated, synthesized, and evaluated using MATLAB and Xilinx Vivado software tools. Performance evaluation is carried out by analyzing hardware resource utilization, including LUTs, Flip-Flops, slices, and RAM blocks, along with execution delay and power consumption. The experimental results demonstrate that the proposed architectures significantly reduce hardware overhead, latency, and energy consumption while improving throughput and scalability compared with conventional DSP implementations. Consequently, the proposed VLSI architectures provide an efficient, flexible, and high-performance hardware solution for real-time DSP applications in wireless communications, multimedia systems, image processing, biomedical signal analysis, and next-generation embedded computing systems.