Design and Implementation of Low Power and High Speed MAC Unit using 8 X 8 Vedic Multiplier for DSP Applications

Abstract

High-speed multiplication is an essential need in contemporary digital arithmetic, especially in domains such as digital signal processing, cryptography, and embedded systems. Conventional multipliers, i.e., array and Booth multipliers, have the disadvantage of increased latency due to sequential and intricate calculations. This project discusses a high-performance hierarchical 8x8- bit Vedic multiplier based on the Urdhva-Tiryagbhyam sutra, which supports parallel multiplication to reduce critical path delays. In this project the design of Multiplier Accumulator Unit (MAC) using Vedic Multiplier is the Ancient Indian Vedic Mathematics technique that has been modified as per technology for improving the performance of mathematical computations. MAC is a part of Digital Signal Processor. The MAC operational speed depends on the speed of multiplier. The proposed MAC unit area is reduced by reducing the number of multiplication and addition operations in the multiplier unit. Multiplier design in this unit is based on Vedic Mathematics. Adder unit is designed by using reversible logic. By the use of this reversible logic technique, power consumption and dissipation is greatly reduced. In Vedic Mathematics, different methods are available for doing multiplication; among those Urdhva Tiryagbhyam is the best approach to do multiplication. Urdhva Tiryagbhyam is a general formula of multiplication applicable to all cases of multiplication. It enables parallel generation of partial products, eliminates unwanted multiplication steps.