Design of Advanced Convolution Using Reversible Logic for Digital Image Processing Applications

Abstract

To perform convolution and filtering processes effectively, the arithmetic system for digital image processing applications must be fast but consume minimal power. The overall performance, power consumption and computational efficiency of Digital Signal Processing systems are significantly influenced by these multipliers and adders. In current VLSI design, reversible logic has been proven to be an effective technique for minimizing energy and improving circuit performance. In this work, an improved convolution structure with reversible logic gates for image processing applications is presented. The architecture is based on efficient reversible gates such as Feynman, Fredkin, TSG, Toffoli, and Peres gates for the optimised arithmetic units used in the convolution and FIR filter operations. Vedic, Wallace Tree and Dadda multipliers are considered as advanced multiplier designs to improve the efficiency of multiplication and reduce propagation latency. The proposed design is designed to minimize the power consumption, waste generation, and complexity of circuits, while improving the performance of the computing system. The hardware modelling and functional verification is done using Verilog HDL and implementation is done using Xilinx ISE/Vivado tools. Experimental study shows that the reversible convolution design can achieve better performance, lower power consumption and higher suitability for real-time digital image and video processing application than the conventional logic-based design.