High-Performance FIR Filters for DSP Systems Via Distributed Arithmetic and RNS with Pipelining and Retiming

Abstract

High-speed digital signal processing (DSP) systems demand efficient finite impulse response (FIR) filter implementations that minimize latency, area, and power consumption while sustaining throughput. This work presents a high-performance FIR filter design based on distributed arithmetic (DA) and the residue number system (RNS), enhanced through pipelining and retiming techniques. By leveraging DA, the proposed architecture eliminates multipliers, reducing hardware complexity, while RNS enables parallel modular computations that increase computational speed. Pipelining and retiming are applied to optimize the critical path and further enhance operating frequency without incurring additional area overhead. Detailed simulations and hardware synthesis demonstrate that the proposed design achieves significant improvements in throughput, latency, and hardware efficiency compared to conventional FIR filter architectures. The results establish the feasibility of combining DA, RNS, and advanced optimization techniques to realize compact, high-speed FIR filters suitable for next-generation DSP applications.