Lightweight MLUT-Based Modular Multiplier Employing ASC and OMS for Cryptographic Systems

Authors

  • 1CHUNDURU NARASIMHA ROHIT, 2V PRASANNA LAXMI Author

DOI:

https://doi.org/10.62643/

Keywords:

Modular Multiplication, Lookup Table (LUT) Optimization, Manipulated Lookup Table Method, HighPerformance Modular Multiplier, High-Speed Computation, Low-Latency Arithmetic, Area-Time Tradeoff, Throughput Optimization, Power-Efficient Design

Abstract

Modular multiplication is a fundamental operation in modern cryptographic algorithms such as RSA, ECC, and lattice-based systems, where achieving high throughput and reduced hardware complexity is critical. Traditional multiplier architectures suffer from large area, long critical paths, and significant power consumption, especially for large operand sizes used in security applications. To address these limitations, this project proposes an optimized Manipulated Lookup Table (MLUT)–based modular multiplier that exploits precomputed residue values stored in a structured LUT. By reorganizing and manipulating LUT entries based on operand bit patterns, the proposed design minimizes multiplier logic, decreases partial product generation time, and significantly reduces propagation delay. The MLUT architecture supports fast modular reduction and incorporates selective LUT activation to reduce unnecessary memory access, thereby improving energy efficiency. Implementation on FPGA shows reduced area utilization, lower dynamic power, and improved operating frequency compared to conventional Montgomery and Booth-based multipliers. The proposed design is highly suitable for lightweight cryptographic processors, IoT edge devices, and real-time embedded security systems requiring high-performance modular arithmetic. The methodology also provides scalability for different modulus sizes and serves as a foundation for advanced extensions such as pipelined MLUT, reconfigurable modulus support, and side-channel-resistant architectures. This work presents an enhanced Manipulated Lookup Table (MLUT) modular multiplier architecture that integrates Anti-Symmetric Coding (ASC) and Odd-Multiple Storage (OMS) to achieve significant LUT memory reduction. The proposed ASC technique leverages the algebraic anti-symmetry property of precomputed residues to eliminate redundant entries, reconstructing them on-the-fly using simple arithmetic operations. Complementarily, OMS stores only odd multiples of operands while generating even multiples through low-cost shift operations. Together, these optimizations reduce LUT storage requirements by up to 75%, minimize LUT access time, and shorten the critical path

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Published

14-05-2026

How to Cite

Lightweight MLUT-Based Modular Multiplier Employing ASC and OMS for Cryptographic Systems. (2026). International Journal of Engineering Research and Science & Technology, 22(2(2), 363-377. https://doi.org/10.62643/