DESIGN AND SIMULATION OF SYSTOLIC ARRAY FOR MATRIX MULTIPLICATION

Abstract

Traditional methods for matrix multiplication often rely on general matrix multiply (GeMM) approaches, where matrices are divided into blocks and processed sequentially or with limited parallelism. These methods face limitations in speed and resource utilization due to the complexity of managing memory and computations, leading to bottlenecks in latency and throughput. Standard implementations typically use multiply-accumulate units arranged in linear or tree structures, which do not fully exploit parallelism and result in slower processing for large matrices. The systolic array architecture overcomes these limitations by arranging processing elements (PEs) in a highly parallel two-dimensional grid, where each element performs multiply-accumulate operations concurrently with data flowing rhythmically between them. This design enables continuous and efficient data movement, minimizing memory access delays and increasing throughput. The modular nature of the array also provides scalability for different matrix sizes, improving performance without significant increases in complexity. Overall, the systolic array-based approach offers a high-speed, efficient, and scalable solution for matrix multiplication, making it suitable for real-time and computation-intensive applications.