LOW ERROR EFFICIENT APPROXIMATE ADDER FOR FPGA

Abstract

In this project we propose a methodology for designing low error efficient approximate adders
for FPGA’s. The proposed methodology utilizes FPGA resources efficiently to reduce the error
of approximate adders. The proposed approach yields two distinct FPGA approximate adders,
the low error and area efficient adder (LEAD) and the Area and Power efficient Adder (APEX).
Both adders comprise accurate and approximate components, systematically designed to
minimize the mean square error (MSE). LEADX provides better quality and APEX provides
low power consumption the other approximate adders. We strategically balancing error
tolerance and aims to maximize performance while minimizing error and propagation delay.
Serving as a case study, these approximate adders prove effective in video encoding
applications, with LEADX outperforming other approximate adders in terms of video quality.