DESIGN AND IMPLEMENTATION OF RADIX-8 UNSIGNED BIT-PAIR RECODING MULTIPLIER FOR IEEE 754 FP16 MANTISSA ARITHMETIC IN AI ACCELERATORS

Abstract

The rapid expansion of Artificial Intelligence (AI) and Deep Neural Network (DNN) applications has significantly increased the demand for high-performance arithmetic units optimized for reduced precision formats such as IEEE 754 half-precision (FP16). In FP16 computation, the mantissa multiplication stage dominates the power, delay, and area characteristics of the floating-point unit. Conventional Booth-based multipliers, including Radix-4 and Radix-8 architectures, introduce unnecessary hardware overhead due to sign extension (SE) and negative encoding (NE), which are redundant for unsigned mantissa operations. This paper proposes a Radix-8 Unsigned Bit-Pair Recoding (BPR) multiplier core specifically optimized for 11×11 FP16 mantissa multiplication. The architecture eliminates sign-extension logic and two’s complement correction terms by employing non-overlapping 4-bit recoding. A Predefined Logic Unit (PLU) generates 1X, 2X, and 3X multiples in parallel using a delayoptimized Carry Select Adder (CSLA). The merged partial product reduction technique compresses the multiplier height from n to n/4, resulting in only three partial product rows for a 12-bit operand. A Binary-to-Excess-1 Converter (BEC)- based Square-Root Carry Select Adder (SQRT-CSLA) is implemented for high-speed final summation. Compared to conventional 8×8 and 16×16 multiplier cores, the proposed 12×12 architecture achieves optimal precision without truncation error while significantly reducing hardware slack, and switching activity. The design is implemented using synthesizable Verilog HDL and verified through exhaustive simulation. Results demonstrate improved area efficiency. making the architecture highly suitable for AI accelerator data paths and embedded floatingpoint units.