DESIGN AND IMPLEMENTATION OF HIGH SPEED HYBRID CARRY SELECT ADDER

Abstract

Adder is considered the principle unit of every arithmetic and logical operation. Carry
select adder (CSLA) is an adder that helps to speed up operations of several arithmetic
function. To further improve the speed, an idea of incorporating more than one high
speed adder logic within a regular CSLA is employed.
This project discusses the design of a hybrid CSLA which utilizes the advantages of
both Kogge Stone adder and look ahead adder (CLA) to obtain higher speed. Kogge
Stone adder is a particular type of Adder and hence it is widely regarded as one of the
high speed addition methods due to faster carry generation.
Look ahead adders are employed in the initial stages of the modified adder to boost its
speed as its computation performance is better if the number of bits are less. A 64-bit
hybrid CSLA is implemented, in Xilinx Spartan 6 FPGA development board. The
modified hybrid carry select adder is found to improve the speed and provides better
results on energy requirement and speed compared to other carry select adders.