System-Level Design and Behavioural Implementation of a Second–Order CT SigmaDelta Modulator

Abstract

This paper presents the system-level design and behavioural implementation of a second-order continuous-time (CT)sigma-delta modulator for high-resolution, low-frequency sensing applications. The modulator architecture is synthesized using the MATLAB Delta-Sigma Toolbox and implemented behaviorally in Cadence Virtuoso using Verilog-A models. A cascade of integrators feed-forward (CIFF) architecture with a 1-bit quantizer and an oversampling ratio (OSR) of 12 is employed to achieve high resolution while maintaining stability. The discrete-time noise transfer function (NTF) is transformed to its continuous-time equivalent using the impulseinvariant transformation with an NRZ feedback DAC pulse. Simulation results demonstrate practical second-order noise shaping. For a 900 mV, 1 Hz sinusoidal input, the modulator achieves an SNR of 86dB, corresponding to an effective number of bits (ENOB) of 14 bits. The influence of the integrator's finite DC gain and limited gainbandwidth product (GBW) on performance is also evaluated. The results validate the proposed modulator architecture for precision low-bandwidth sensing front-end applications.