DESIGN AND ANALYSIS OF A 4-BIT ASYNCHRONOUS COUNTER USING SENSE-AMPLIFIER BASED FLIP-FLOPS

Abstract

The Cadence EDA tool was used for all design and simulation work on the Sense-Amplifier- Based Flip-Flop (SAFF) for low-voltage operation. Traditional flip-flop designs frequently experience issues including poor noise margins, increased latency, and unreliable switching as contemporary VLSI systems continue to operate at lower supply volages to reduce power consumption. These problems are mitigated by sense-amplifier-based flip-flops, which are ideal for low-voltage applications because they can precisely detect minute voltage changes.The design and implementation of a 4-bit asynchronous counter employing an is the main goal of this project. This project compares the performance of a transmission-gate flip-flops (TGFFs) with a 4-bit asynchronous counter developed using the suggested SAFF architecture. The synchronous counter's design guarantees simultaneous switching and prevents the ripple delay present in asynchronous counters because all of its flipflops are powered by a single clock. The Cadence Virtuoso environment is used for the evaluation, which focuses on crucial factors including power consumption, propagation latency, and dependability at lower supply voltages. According to simulation studies, the SAFF-based counter outperforms the TGFF-based design in terms of power consumption, speed, and dependability at low voltages. Overall, this effort shows that the suggested SAFF-based counter is an appropriate and economical choice for near- threshold and low-power VLSI applications.