DESIGN AND SIMULATION OF MOD-10 SYNCHRONOUS COUNTERS USING DUAL-LATCH FLIP-FLOPS

Abstract

In this project, a MOD-10 synchronous counter using twin latch flip-flops is designed and simulated. One common sequential circuit is the MOD-10 counter, which counts from 0 to 9 before resetting to zero. In contrast to traditional flip-flop-based counters, the suggested design uses dual latch flip-flops with sensing and latching stages to enhance timing performance. By ensuring that all state changes take place concurrently with the clock edge, synchronous operation minimises propagation time and prevents ripple effects. Dual latch flip-flops separate data capture from output transitions, resulting in glitch-free operation and improved synchronisation. After the count reaches decimal nine, reset logic is used to guarantee correct rollover. To ensure proper counting behaviour, digital design tools are used to construct and simulate the entire counter circuit.