DESIGN A COMPARATOR WITH LOW KICKBACK

Abstract

This brief presents a three-stage comparator and
its modified version to enhance speed and
Reduce kick back noise. Compared to
conventional two-stage comparators, the
proposed three-stage design introduces an
additional amplification stage that increases
voltage gain and significantly improves
operational speed. While traditional two-stage
comparators typically utilize pMOS input pairs
in the regeneration stage, this three-stage design
employs nMOS input pairs in both the
amplification and regeneration stages, benefiting
from higher carrier mobility to further enhance
speed. In the modified version of the three-stage
comparator,
A CMOS input pair is used in the
amplification stage. This configuration
effectively cancels out the kickback noise from
the nMOS transistors through the opposing
kickback of the pMOS devices. Additionally, the
modified design incorporates an extra signal
path in the regeneration stage, further boosting
the comparator’s speed. For accurate
benchmarking, both the traditional two-stage
and the proposed three-stage comparators were
implemented using the same CMOS process.
Measured results demonstrate that the modified
comparator improves speed and reduces
kickback noise by a factor of ten. Notably, these
enhancements are achieved without increasing
the input-referred offset or noise.