DESIGN AND IMPLEMENTATION OF ERROR DETECTION AND CORRECTION SYSTEM FOR SEMICONDUCTOR MEMORY APPLICATIONS

Abstract

On behalf of technology scaling, on-chip
memories in a die undergoes bit errors because
of single events or multiple cell upsets by the
ecological factors such as cosmic radiation,
alpha, neutron particles or due to maximum
temperature in space, leads to data corruption.
Error detection and correction techniques
(ECC) recognize and rectify the corrupted data
over communication channel. In this paper, an
advanced error correction 2-dimensional code
based on divide-symbol is proposed to weaken
radiation-induced MCUs in memory for space
applications. For encoding data bits, diagonal
bits, parity bits and check bits were analyzed
by XOR operation. To recover the data, again
XOR operation was performed between the
encoded bits and the recalculated encoded bits.
After analyzing, verification, selection and
correction process takes place.
Extension:
A typical system-level technique to harden
memory against multiple bit upsets (MBUs)
would be the use of error correction codes
(ECCs) for enhanced correction capabilities.
Building updated ECCs with low redundancy
and correction of errors however has be a
significant issue, especially about adjacent
ECCs. Present MBU mitigation codes
concentrate primarily on correcting up to 3-bit
explosive errors. The amount of impaired bits
will quickly extend to even more than 3 bit as
that of the software scales as well as the cell
interval gap decrease. Consequently, the
earlier approaches are not adequate to meet the
criterion for durability in harsh conditions. In
this article, a technique for 4-bit bursting bug
fix (BEC) codes was introduced with a
Multiple bit error detection and correction
(MBEDC) codes. Initially you define the
interface principles, then you create a search
algorithm for locate the codes that correspond
to both the rules. Usable are the 4-bit BEC H
matrices with MBEDC codes. Any additional
parity check bits were needed compared with
such a BEC 3-bit code. That efficiency of 4-bit
BEC was also substantially enhanced by
adding the latest algorithm with existing 3-bit
BEC codes. A project with verilog HDL
would be built. The Simulation & Synthesis
Xilinx ISE method is used.