DESIGN AND ANALYSIS OF HIGH SPEED WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDRESS FOR VLSI CIRCUIT DESIGN

Abstract

Multiplication is a fundamental operation in
digital circuits, and its efficiency directly
impacts the performance of high-speed
computing systems. The Wallace Tree
Multiplier (WTM) is widely used in Very
Large Scale Integration (VLSI) designs due to
its parallel reduction capability, significantly
reducing delay compared to conventional
multipliers. However, the accumulation of
partial products in WTM still introduces
latency and power consumption challenges. To
further enhance speed and power efficiency,
this study proposes a high-speed Wallace Tree
Multiplier integrated with Parallel Prefix
Adders (PPA). The PPA optimizes the final
addition stage, reducing propagation delay and
improving overall performance. The proposed
design is implemented and analyzed in terms
of delay, area, and power consumption,
demonstrating superior efficiency over
traditional array multipliers and conventional
Wallace multipliers. The results indicate that
the proposed approach achieves significant
reductions in critical path delay and power
dissipation, making it ideal for highperformance VLSI applications.