VLSI IMPLEMENTATION OF ADAPTIVE FIR FILTER USING DA WITH LOW POWER AND LOW AREA

Abstract

The growing demand for efficient digital
signal processing (DSP) in wireless
communication systems has led to a 30%
increase in research on advanced filter designs
like Finite Impulse Response (FIR) filters. FIR
filters are crucial for reducing noise and
enhancing signal quality, with over 50% of
modern wireless systems relying on them.
However, traditional FIR filters using basic
adder-based architectures face limitations in
speed and power efficiency, leading to
suboptimal performance in high-frequency
communication systems. Conventional FIR
filters implemented with basic adders suffer
from high power consumption and delay,
which become significant bottlenecks in realtime communication applications. This paper
introduces a novel approach using Distributive
Arithmetic (DA)-based Look-Up Table (LUT)
architectures with parallel registers for FIR
filters, which improves computational
efficiency. By leveraging DA-LUT and
parallel processing, the proposed FIR filter
design reduces latency, power consumption,
and area while maintaining high performance,
making it ideal for high-speed wireless
communication systems.