Design and Implementation of Systolic Multiplier Using Hybrid Multiplexer Dependent Adder
DOI:
https://doi.org/10.62643/Keywords:
Systolic Multiplier, Hybrid Multiplexer, VLSI- Very large scale Integration, Digital Signal Processing, BaurnMultiplier, Wallace Multiplier, Razor Flipflop, ReliabilityAbstract
The implementation of a systolic multiplier using a hybrid multiplexer-dependent adder offers significant improvements in computational speed and efficiency, particularly in VLSI front-end design. According to recent studies, the global digital signal processing(DSP)marketisexpectedto reach$25.37billionby2026, growing at a compound annual growth rate (CAGR) of 9.4%. Multipliers are fundamental components in DSP systems, and efficient multiplier designs are critical for enhancing performance, especially in real-time applications. However, traditional multiplier designs, like Baurn and Wallace multipliers, suffer from high power consumption, increased latency, and complex architectures that make them unsuitable for modern VLSI applications. In this work, we propose a novel systolic multiplier that leverages a multiplexer- dependent adder composed of a 2-to-1 multiplexer and a full adder. This design is further enhanced by integrating a systolic array architecture and a Razor Flipflop for error detection and correction. The use of a multiplexer-dependent adder reduces the overall complexity of the multiplier, while the systolic array ensures high- speed parallel processing. The Razor Flipflop provides error tolerance, enabling the system to maintain performance undervariable operating conditions. This novel combination significantly improvesspeed,reducespowerconsumption,andenhancesreliability in VLSI implementations.
Downloads
Published
Issue
Section
License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.