Design of Multiply Accumulate Unit with Self-Error Correction and Accumulation Modules

Abstract

Multiply-Accumulate Units (MACs) are essential components in digital signal processing (DSP) and machine learning algorithms, widely employed in convolutional neural networks (CNNs) and other computations. Current research shows that enhancing the efficiency of MAC units can lead to a 20-30% reduction in computation time, while power consumption can decrease by 15-25%, directly benefiting various high-performance systems. Traditional MAC units rely on simple adders and multipliers, which suffer from limited precision, slower speed, and higher power consumption in large-scale implementations. This work presents a novel MAC design incorporating a Modified Booth Multiplier and an Error Correctable Carry Look Ahead Adder (ECCLA). The Modified Booth Multiplier enhances the multiplication speed by reducing partial products, while the ECCLA improves precision and fault tolerance during accumulation. The proposed MAC architecture also features self- error correction mechanisms that detect and correct arithmetic errors, ensuring improved performance and reliability in error-sensitive applications. Experimental results demonstrate that the proposed MAC design achieves up to 35% faster computation speed and 20% more accurate results compared to traditional architectures.