FPGA Implementation of a Bus Ticketing System using Verilog HDL

Abstract

The Verilog-based automatic bus ticketing system enhances public transportation by automating fare collection, reducing human intervention, and improving passenger convenience. Implemented on an FPGA platform, the system integrates key modules for passenger authentication, fare calculation, and transaction logging. A smart card reader ensures seamless validation, while a digital display provides real-time fare updates. Simulation results demonstrate efficiency in handling multiple passengers with high accuracy. The FPGA-based approach offers scalability, security, and potential IOT integration, positioning it as a reliable solution for modern urban transit systems.