Analysis of Power, Delay, and Area in Full Adder Circuits Across CMOS Nodes

Abstract

As technology advances, digital circuits are becoming more complex, requiring efficient and power-conscious arithmetic units. This study explores the performance of full adders implemented with different CMOS technologies, focusing on power consumption, propagation delay, and area efficiency. Using simulation tools like Tanner EDA , we compare 45 nm and 90 nm technology nodes to understand the trade offs between speed, power, and area. Our findings indicate that hybrid full adders provide a better balance between power efficiency, performance, and area utilization, making them suitable for modern low-power applications.