Efficient Clock Gating Techniques For Power Management In Domino Logic Using 16nm Technology

Abstract

paper presents a novel approach for reducing power consumption in CMOS domino logic. The proposed method integrates clock gating along with an output retention mechanism. The clock signal is supplied to the domino logic only when the circuit is active, while it is bypassed during standby mode to conserve power, ensuring that the circuit’s state remains preserved. A 2:1 multiplexer is employed for both clock gating and state retention. Simulations have been conducted on a 2-input NAND gate and a 1-bit conventional full adder cell using 16nm CMOS technology. The proposed design achieves an average power reduction of 99.37% compared to standard domino logic. However, propagation delay experiences a slight increase of approximately 4.53%. The circuit area expands by four additional transistors per domino module.