DESIGN OF 64-BIT SIGNED MAGNITUDE COMPARATOR USING FPGA FOR IOT APPLICATIONS

Abstract

The increasing demand for high-speed and efficient data processing in IoT applications necessitates the development of optimized hardware comparators. This project presents a Novel High-Speed 64-bit Signed Magnitude Comparator (SMC) designed using Verilog HDL, targeting applications such as sorting techniques, digital communication devices, data converters, and processor address decoding units. The proposed design follows a hierarchical approach, where the Most Significant Bit (MSB) of two 64-bit signed numbers, represented in two’s complement form, is compared first, followed by the remaining bits to determine whether the numbers are equal, greater, or lesser. The 8-bit signed comparator serves as the fundamental building block (Leaf Cell) of the design and is hierarchically extended to 16-bit, 32-bit, and finally 64-bit using structural modelling in Verilog HDL. The proposed 64-bit SMC achieves a significantly less delay, demonstrating its efficiency in high-speed computation. The design has been functionally verified, synthesized, and implemented in Xilinx Vivado