LOW POWER AREA-EFFICIENT 16-BIT ALU WITH LOWPOWER FULL ADDER USING ACCELERATOR

Abstract

The Arithmetic and Logic Unit (ALU) is a fundamental component of digital processors, embedded systems, controllers, and digital signal processing applications. As computational requirements increase, designing an ALU with reduced power consumption, efficient hardware utilization, and improved processing throughput becomes an important challenge in Very Large-Scale Integration (VLSI) design. Conventional ALU architectures may experience carry propagation delay during arithmetic operations and limited throughput when multiple independent operations are executed sequentially. To address these challenges, this project proposes a low-power-oriented, area-efficient 16-bit ALU using an XNOR-based full-adder formulation and a two-lane hardware accelerator. The proposed system is developed using a hierarchical architecture consisting of a one-bit full adder, a 16-bit ripple-carry adder, a multifunctional ALU, and two parallel ALU processing lanes. The XNOR-oriented full-adder formulation provides an alternative Boolean representation of conventional sum and carry operations, while the ALU supports arithmetic operations such as addition, subtraction, increment, and decrement, along with logical operations, bit shifting, and comparison functions. The two-lane accelerator enables independent operations to be evaluated concurrently, and a multiplexer selects the required output. The design is described using synthesizable Verilog HDL and is intended for functional verification through Xilinx ISE and ISim tools. Three verification scenarios are considered to test arithmetic operations, logical and shift operations, comparison functions, and parallel accelerator behavior. The proposed architecture provides a modular and scalable foundation for FPGA-based digital system design, with potential applications in embedded processors, IoT devices, digital signal processing, and hardware acceleration. Its performance can be evaluated using hardware resource utilization, propagation delay, and power estimation. Although parallel processing can improve throughput, duplicating ALU hardware may increase area and active power consumption. Similarly, the XNOR-oriented formulation alone does not guarantee lower power consumption in an FPGA implementation because synthesis tools may map equivalent Boolean expressions into the same hardware resources. Therefore, comparative synthesis and power analysis under consistent implementation conditions are necessary to establish the actual benefits of the proposed design.