ADAPTIVE PRECISION-SCALABLE MULTIPLIER ARCHITECTURE FOR LOW-POWER, AREA-EFFICIENT, AND HIGH-PERFORMANCE VLSI APPLICATIONS

Abstract

Multipliers are fundamental arithmetic components in digital signal processing, image processing, machine learning accelerators, communication systems, and embedded VLSI applications. As modern integrated circuits demand higher computational performance while maintaining low power consumption and reduced silicon area, the design of efficient multiplier architectures has become a critical research challenge. This paper presents an Adaptive Precision-Scalable Multiplier Architecture aimed at achieving low-power operation, area efficiency, and high computational performance for advanced VLSI systems. The proposed architecture dynamically adjusts computational precision according to application requirements, enabling efficient utilization of hardware resources and minimizing unnecessary switching activity. By incorporating scalable arithmetic units, adaptive control logic, and optimized partial-product generation techniques, the multiplier supports multiple precision modes while maintaining high processing speed and computational accuracy. The architecture further employs power-aware design methodologies and resource-sharing mechanisms to reduce circuit complexity and energy consumption. Experimental evaluation demonstrates significant improvements in power efficiency, area utilization, propagation delay, and throughput when compared with conventional fixedprecision multiplier designs. Results indicate that the proposed adaptive precision-scalable multiplier achieves substantial reductions in power consumption and hardware resources while providing flexible performance scalability for diverse computational workloads. The architecture is particularly suitable for energyconstrained and high-performance VLSI applications requiring adaptive arithmetic processing. Consequently, the proposed design offers an effective solution for next-generation low-power digital systems, portable electronics, edge computing devices, and intelligent hardware accelerators.