A Secure FPGA-Based Lightweight AES Architecture with DFA Countermeasures for IoT Applications

Abstract

The IoT edge nodes are usually designed with stringent requirements to minimise space and power consumption and cost, and of course, in any case, to provide reliable security for the data they collect or transport. AES can be fully parallelised to give high security guarantees but the logic resource requirement is greater than the capacity of most of the edge hardware. A lightweight AES-128 (LWAES) core is proposed and assessed on a Xilinx Artix-7 FPGA (xc7a35tcpg236-1) in this research. The datapath is sequential, and resources are shared. Finally, we repeat the main computation of each ciphertext and compare it to the original one to check for weaknesses introduced in the process, using an online DFA countermeasure. The synthesis results show that use of Slice LUTs is reduced by 60.7% from the 9,505 LUTs of a standard parallel AES-128 core to 3,733 LUTs for the lightweight core. The total on-chip power consumption is decreased from 2,579.21 W to 639.25 W (75.2%). The fault detection logic requires 0.35 W and is implemented with one additional I/O pin; there is no increase in the number of LUTs or registers. Our findings show that there is a potential to accumulate extensive DFA resilience on top of a light-weight AES core without incurring significant area overhead, which is promising for IoT security applications that are constrained by power and area. Keywords: AES, FPGA, Differential Fault Analysis, lightweight cryptography, IoT security, concurrent error detection, Verilog HDL