Design of a High-Performance MAC Unit Using Hybrid Compressor-Based Multiplier and Efficient Adders

Abstract

The Multiply-Accumulate (MAC) unit is one of the most critical arithmetic components in digital signal processing (DSP), image processing, and artificial intelligence applications, where high speed, low power consumption, and efficient hardware utilization are essential. This paper proposes an optimized MAC architecture that integrates a hybrid compressor-based multiplier in the multiplication stage with a Carry Save Adder (CSA) for the accumulation process. The use of higher-order compressors (4:2, 5:2 and 15:4) minimizes partial-product reduction delay, while the CSA performs intermediate additions without immediate carry propagation, thereby improving overall computational performance. The proposed 16- bit MAC architecture is implemented in Verilog HDL, functionally verified, and synthesized using the Xilinx Vivado tool, and is compared against a conventional MAC design that employs a Carry Look-Ahead Adder (CLA). Experimental evaluation demonstrates that the proposed MAC achieves reduced logic resource utilization (446 LUTs versus 451 LUTs), lower propagation delay (1.43 ns versus 1.51 ns), and marginally lower power consumption (39.579 W versus 39.581 W) compared with the existing CLA-based architecture. These improvements make the proposed design well suited for high-speed, low-power FPGA-based DSP processors and real-time signal-processing systems. Keywords—Multiply-Accumulate (MAC) unit; Hybrid Compressor; Carry Save Adder (CSA); Carry Look-Ahead Adder (CLA); Compressorbased Multiplier; VLSI; Verilog HDL; FPGA; Low-Power Design; Xilinx Vivado.