DESIGN OF A RECONFIGURABLE APPROXIMATE MULTIPLIER WITH TUNABLE ACCURACY

Abstract

In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major components, namely, switching power and internal power. In this paper, we present a low-power design for an accuracy-controllable multiplier. Multiplication is a key fundamental function for many error-tolerant applications. Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes an accuracycontrollable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial product tree of the multiplier is approximated by the proposed tree compressor. A multiplier design is implemented by employing the carry maskable adder and the compressor. Compared with a conventional multiplier, the proposed multiplier reduced power consumption. The implementation, synthesis and simulation are executed and noted in the Xilinx-ISE in Verilog HDL language.