POWER OPTIMIZATION OF BOOTH MULTIPLIER USING CLOCK GATING AND OPERAND ISOLATION TECHNIQUES

Abstract

The increasing demand for portable electronics, embedded processors, digital signal processing (DSP) systems, and communication devices has made low-power VLSI design an important research area. Among arithmetic units, multipliers are frequently used in computationally intensive operations and can contribute considerably to switching activity and dynamic power consumption. Therefore, optimizing multiplier architectures is essential for achieving energy-efficient digital systems without compromising computational accuracy and performance. The present work focuses on the power optimization of a signed Booth multiplier using Clock Gating and Operand Isolation techniques. The multiplier employs Radix-4 Modified Booth Encoding to reduce the number of generated partial products, followed by partial-product reduction and a parallel-prefix based final addition stage. Clock gating is incorporated to suppress unnecessary clock transitions in inactive sequential elements, whereas operand isolation prevents unwanted changes from propagating through the computational datapath when multiplication is not required. The complete architecture is described using Verilog HDL and evaluated through functional simulation and FPGA-oriented synthesis using Xilinx design tools. The implementation is analyzed in terms of functional correctness, hardware utilization, timing, and power-related design considerations. The synthesized design utilizes 135 slice LUTs, 26 I/O resources, and one BUFG/BUFGCTRL resource, with a reported total data-path delay of 7.904 ns. The results demonstrate that combining Booth encoding, efficient partial-product reduction, parallel-prefix addition, clock gating, and operand isolation provides a practical architecture for low-power digital arithmetic applications. The proposed approach is suitable for DSP processors, embedded systems, portable electronics, and other power-sensitive VLSI applications. Keywords: Booth Multiplier, Radix-4 Modified Booth Encoding, Clock Gating, Operand Isolation, Low-Power VLSI, Verilog HDL, Parallel-Prefix Adder, Dynamic Power, FPGA.