Design of Hybrid Memory Logic Based BIST for Memory Testing

Abstract

Embedded memories occupy a dominant fraction of contemporary system-on-chip area and are increasingly exposed to manufacturing variation, timingsensitive defects, coupling effects, and in-field degradation. This paper presents a Hybrid Memory Logic Based Built-In Self-Test (HML-BIST) architecture that combines deterministic March operations with logic-BIST-style linear-feedback shift-register patterns in a unified finite-state-machine-controlled framework. The design contains a dual-mode test-pattern generator, ascending/descending/random address generation, a 256 × 8 synchronous SRAM under test, a bitwise response analyzer, and a location-aware fault register. Deterministic passes target stuck-at, transition, coupling, address-decoder, retention, and read/write faults, while pseudorandom stress targets neighborhood pattern-sensitive and dynamic faults. The Verilog RTL was evaluated using Xilinx Vivado 2023.1 XSim and synthesized for an Artix-7 XC7A100T FPGA. The implementation uses 187 LUTs, 94 flip-flops, one RAMB18E1 block, and no DSP resources, closes timing at 200 MHz, and reports 42.0 ms test time, 12.4 mW dynamic power, and 3.2% peripheral-logic area overhead. Recalculation of the detailed injection table gives 3,948 detections from 4,096 injected instances, corresponding to 96.4% count-consistent overall coverage across eight fault categories. The architecture therefore provides a compact, at-speed, fault-localizing platform suitable for reusable embedded-memory test and future safetyoriented SoC integration.