Posit-Based Arithmetic Unit Design Using HUB Number Representation

Abstract

The rapid advancement of digital arithmetic architectures has increased the demand for high-speed, low-power, and accuracy-efficient numerical computing systems. Traditional binary arithmetic units often suffer from limitations such as rounding errors, overflow, underflow, and high hardware complexity when used in scientific computing, signal processing, embedded systems, and artificial intelligence applications. To overcome these limitations, the proposed HUB Meets Posit: Arithmetic Units Implementation introduces an efficient arithmetic architecture based on the Posit number system. The Posit format provides better dynamic range, improved numerical accuracy, and reduced hardware overhead compared to conventional floating-point representations. The proposed system implements arithmetic units such as addition, subtraction, multiplication, and division using posit-based computation techniques. It integrates decoding, regime extraction, exponent processing, fraction operation, normalization, and encoding modules to perform accurate arithmetic operations. The implementation improves computational precision, reduces memory usage, and enhances performance for hardware-based numerical applications. By combining posit arithmetic with optimized hardware design methodologies, the proposed architecture provides an efficient alternative for modern digital processing systems. The system is highly suitable for machine learning accelerators, digital signal processing, embedded processors, scientific computing, and low-power hardware implementations.