Design and Performance Evaluation of a Low-Power 4×4 Binary Multiplier Using Dadda Reduction and Efficient Full Adder Architecture

Abstract

Low-power and high-speed arithmetic circuits play a vital role in modern digital signal processing, embedded systems, and VLSI applications. Multipliers are one of the most important components in digital hardware systems, as they directly affect the overall performance, power consumption, and computational efficiency of processors and arithmetic logic units. Conventional multiplier architectures often suffer from increased power dissipation, propagation delay, and hardware complexity, which limit their efficiency in portable and high-performance electronic devices. The proposed “Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder” aims to develop an efficient multiplier architecture that reduces power consumption and improves computational speed using the Dadda multiplication technique and optimized full adder circuits. The proposed design utilizes the Dadda reduction algorithm to minimize partial product reduction stages, thereby reducing hardware complexity and propagation delay. In addition, optimized full adder circuits are implemented to achieve lower switching power and improved arithmetic performance during multiplication operations. The combination of the Dadda algorithm and optimized full adders enhances speed, area efficiency, and energy savings compared to conventional array and Wallace tree multipliers. The multiplier design is suitable for low-power VLSI systems, embedded processors, digital signal processing applications, and portable electronic devices. Simulation and performance analysis demonstrate that the proposed multiplier architecture achieves reduced power consumption, faster computation, and improved efficiency, making it an effective solution for modern low-power digital system design.