FR-FCFS Reordering DDR Memory Controller with Reorder Buffer for Improved Bank-Level Parallelism

Abstract

Conventional in-order, close-page DDR SDRAM controllers service requests strictly in arrival order and precharge (close) the accessed row after every transaction, regardless of whether a subsequent request targets the same row — a simple, easily verified policy that forfeits rowlocality and bank-parallelism opportunities present in realistic memory traffic. This paper presents a First-Ready, First-Come-First-Served (FR-FCFS) DDR controller that replaces the single global finite-state machine of the inorder design with independent per-bank PRECHARGE/ACTIVATE/OPEN state, an open-page policy that keeps rows open across accesses, and a small command-reordering buffer that prioritizes row-hit ("firstready") requests ahead of row-miss requests while preserving first-come-first-served ordering among equallyready requests. Both controllers are implemented in synthesizable Verilog, functionally verified, and synthesized/implemented on a Xilinx Artix-7 FPGA (xc7a100tcsg324-1, Vivado 2019.2). Post-implementation results show the proposed controller uses substantially more area (185 LUTs, 157 registers versus 34 LUTs, 59 registers) and a longer single-path critical delay (7.907 ns versus 3.818 ns) than the in-order baseline — an outcome that, taken at face value, appears to favor the simpler design. This paper argues, and demonstrates through architectural analysis, that static single-path timing analysis is the wrong lens for evaluating a reordering memory controller: FRFCFS's benefit is sustained throughput under concurrent multi-bank traffic, where one bank can precharge or activate while another simultaneously services a column access, a scenario the in-order controller's fully serialized single-bank FSM cannot exploit at all regardless of its faster single-path delay. The paper characterizes both the true area/delay/power cost of the added reordering logic and the traffic conditions under which FR-FCFS's bank-level parallelism converts that cost into a net system throughput gain. Keywords: DDR SDRAM controller, FR-FCFS scheduling, memory controller, bank-level parallelism, open-page policy, reorder buffer, FPGA implementation