Booth-Encoded versus Baugh-Wooley Signed Multiplication: An FPGA Area-Delay Comparative Study

Abstract

Signed multiplier design must handle two's-complement sign extension correctly while minimizing the number of partial-product rows requiring summation, since both the row count and the summation network's topology directly determine area and critical-path delay. This paper compares an Baugh-Wooley signed multiplier, which avoids explicit sign-extension logic by complementing the last partial-product row and column and applying a fixed correction constant, but still generates a full 8 partialproduct rows summed through a flat sequential chain of 16- bit ripple adders, against an  Modified Booth radix-4 signed multiplier, which uses 3-bit overlapping operand groups to select each partial product from  , halving the partial-product row count to 4 and summing them through a 2-level addition tree instead of a flat 7-stage chain. Both designs are captured in synthesizable Verilog, exhaustively functionally verified with Icarus Verilog across all 65,536 possible signed 8-bit input pairs, and synthesized/implemented on a Xilinx Artix-7 FPGA (xc7a100tcsg324-1, Vivado 2019.2). Post-implementation results show the Booth multiplier uses 39% fewer LUTs (91 vs. 150) and is 32% faster (7.092 ns vs. 10.379 ns) than the Baugh-Wooley baseline, with correspondingly higher throughput and lower energy per operation. Unlike the companion GDI, TSPC, and mixed-logic case studies in this line of work — where standard-cell-level transistor-count reductions are absorbed by FPGA LUT-based technology mapping — this paper shows that Booth encoding's architectural benefit (fewer partial-product rows and a shallower, tree-structured summation network) survives FPGA implementation intact, because it reduces the number of addition operations rather than only the transistor count of an individual cell, directly translating into fewer LUTmapped adder stages regardless of target technology. Keywords: Modified Booth encoding, Baugh-Wooley multiplier, signed multiplication, radix-4 Booth recoding, partial product reduction, FPGA implementation, highspeed multiplier design