Reconfigurable Symmetric Dyadic Filter VLSI Architecture for HighFidelity Medical Image Fusion

Abstract

The rapid growth of medical imaging has significantly increased the volume of diagnostic data generated worldwide, with recent healthcare reports indicating that more than 5 billion medical imaging examinations are performed annually and nearly 80% of clinical decisions rely on imaging-based diagnosis. However, existing wavelet-based Medical Image Fusion (MIF) systems often rely on fixed filter architectures that require many arithmetic units, memory resources, and dedicated hardware blocks, resulting in increased area utilization, power consumption, and processing latency. These limitations reduce scalability and restrict real-time deployment in portable and resource-constrained medical imaging devices. To address these challenges, this work proposes a Reconfigurable Symmetric Dyadic Filter (SDF) VLSI Architecture for High-Fidelity MIF, designed to provide flexible and efficient wavelet decomposition and reconstruction. The proposed architecture incorporates a controller-driven reconfigurable framework, filter coefficient ROM, optimized Multiply-Accumulate (MAC) unit, internal register structure, and coefficient storage RAM for approximation and detail coefficients. The controller dynamically configures filter operations, enabling adaptive processing while minimizing hardware redundancy. The symmetric dyadic filtering structure significantly reduces computational complexity, memory access overhead, and critical path delay, thereby improving throughput and energy efficiency. By supporting high-speed wavelet processing with reduced hardware resources, the proposed SDF architecture enables accurate and real-time medical image fusion while achieving enhanced image quality, lower power consumption, and improved VLSI implementation efficiency suitable for next-generation healthcare and IoMT-based diagnostic systems.