FPGA-BASED LIGHTWEIGHT HYBRID PHYSICAL UNCLONABLE FUNCTION FOR SECURE DEVICE AUTHENTICATION USING ARBITER AND RING OSCILLATOR ARCHITECTURES

Abstract

The rapid growth of Internet of Things (IoT), embedded systems, and edge computing devices has increased the demand for robust hardware security solutions capable of preventing cloning, counterfeiting, and unauthorized access. Physical Unclonable Functions (PUFs) have emerged as an effective hardwarebased security mechanism by exploiting inherent manufacturing variations in integrated circuits to generate unique device identities. This paper presents the design and FPGA implementation of a lightweight Hybrid Physical Unclonable Function (PUF) that combines the advantages of Arbiter PUF and Ring Oscillator (RO) PUF architectures. The proposed hybrid structure utilizes delaybased characteristics from the Arbiter PUF and frequency-based variations from the Ring Oscillator PUF to generate highly unique and reliable challenge– response pairs. The outputs from both PUF modules are combined through an XOR-based response generation mechanism to enhance randomness, uniqueness, and resistance against modelling attacks. The architecture is implemented using Verilog HDL and validated through simulation and FPGA synthesis. Experimental analysis demonstrates improved security performance, enhanced reliability, and reduced hardware resource utilization compared to conventional standalone PUF architectures. The floorplan-aware implementation further improves response stability and minimizes routing-induced variations. The proposed design offers a low-area, costeffective, and secure authentication solution suitable for FPGA-based embedded systems, IoT devices, and next-generation hardware security applications.