DESIGN AND FPGA IMPLEMENTATION OF A POWEREFFICIENT VCO-BASED ANALOG-TO-DIGITAL CONVERTER USING CURRENT MODE LOGIC ARCHITECTURE AND FINFET POWER GATING

Abstract

Analog-to-Digital Converters (ADCs) play a crucial role in modern electronic systems by enabling communication between analog environments and digital processing platforms. Conventional ADC architectures such as Flash, Successive Approximation Register (SAR), Pipeline, and Sigma-Delta ADCs often face challenges related to high power consumption, increased hardware complexity, and limited scalability in advanced semiconductor technologies. To address these limitations, this paper presents a power-efficient VoltageControlled Oscillator (VCO)-based Analog-to-Digital Converter utilizing Current Mode Logic (CML) architecture and FinFET-based power gating techniques. The proposed system converts the input analog voltage into a corresponding oscillation frequency using a CML-based VCO, which offers high-speed operation, improved signal integrity, and reduced propagation delay. The generated frequency is processed through an edge detector, digital counter, and output register to produce the final digital output code. To minimize standby and leakage power consumption, FinFET-based power gating transistors are incorporated into the architecture, enabling efficient power management during inactive operating conditions. The complete design is modeled using Verilog HDL and implemented on an FPGA platform using Xilinx Vivado tools for functional verification and performance evaluation. Experimental analysis demonstrates significant improvements in power efficiency, reduced leakage current, enhanced operating speed, and optimized hardware utilization compared to conventional ADC implementations. The proposed architecture is highly suitable for low-power communication systems, biomedical devices, sensor networks, and Internet of Things (IoT) applications where energy efficiency and high-speed data conversion are critical requirements.