DESIGN AND FPGA IMPLEMENTATION OF HIGHPERFORMANCE 64-BIT HYBRID ADDER ARCHITECTURES FOR OPTIMIZED POWER-DELAY-AREA PERFORMANCE

Abstract

Modern digital systems require arithmetic circuits that provide high speed, low power consumption, and efficient hardware utilization. Adders are among the most critical components in processors, digital signal processors, communication systems, and embedded platforms, directly influencing overall computational performance. Conventional adder architectures such as Ripple Carry Adders (RCA), Carry Lookahead Adders (CLA), Carry Select Adders (CSLA), Carry Skip Adders (CSKA), and Parallel Prefix Adders exhibit inherent trade-offs between propagation delay, power consumption, and area utilization. To address these limitations, this paper presents the design, implementation, and comparative evaluation of several highperformance 64-bit hybrid adder architectures based on hierarchical partitioning and hybridization techniques. The proposed designs combine the advantages of Carry Lookahead, Carry Select, Carry Skip, and Kogge-Stone Adders to achieve improved arithmetic performance while maintaining balanced hardware complexity. Multiple hybrid architectures, including CLA (32) + KSA (32), CSLA (32) + KSA (32), (CSLA (16) + KSA (16)) + KSA (32), (CSLA (16) + KSA (16)) + CSKA (32), RCA (32) +CSKA (32), and other hierarchical combinations, are modeled using Verilog HDL and synthesized using Xilinx Vivado targeting FPGA platforms. Functional verification and synthesis analysis are performed to evaluate propagation delay, power consumption, area utilization, and overall Power-Delay-Area (PDA) performance. Experimental results demonstrate that hybrid architectures significantly reduce critical path delay while achieving better resource utilization compared to conventional adder designs. The hierarchical hybrid approach provides an effective solution for high-speed arithmetic operations in modern VLSI systems, processors, signal processing units, and FPGA-based computing applications.