A NOVEL DOUBLE-TAIL DYNAMIC COMPARATOR FOR LOWPOWER HIGH-SPEED ADCS

Abstract

Analog-to-Digital Converters (ADCs) are essential components in modern communication, signal processing, biomedical, and embedded systems. The performance of an ADC largely depends on the efficiency of its comparator, which acts as the decisionmaking element during signal conversion. Conventional dynamic comparators provide high speed and low static power consumption but suffer from increased delay, limited operation at low supply voltages, and higher power dissipation. This paper presents the design and analysis of a low-power highspeed dynamic comparator based on a modified double-tail architecture. The proposed comparator enhances regenerative feedback by incorporating additional cross-coupled control transistors, thereby significantly reducing latch regeneration time and improving comparison speed. The architecture operates efficiently under low-voltage conditions while maintaining low power consumption and high accuracy. Detailed analysis of comparator delay, power consumption, and operating characteristics is carried out using VLSI design methodologies. Simulation results demonstrate that the proposed design achieves faster decisionmaking, reduced propagation delay, lower power dissipation, and improved overall performance compared to conventional dynamic comparators. The proposed comparator is suitable for high-speed and low-power ADC applications used in portable electronics, wireless communication systems, biomedical instruments, and Internet of Things (IoT) devices.