DESIGN AND IMPLEMENTATION OF AN ADC/DAC-FREE WALSH–HADAMARD TRANSFORM BASED NEURAL NETWORK ACCELERATOR USING BIT-PLANE PROCESSING FOR LOW-POWER EDGE INTELLIGENCE APPLICATIONS

Abstract

The rapid growth of artificial intelligence and deep neural networks has created a significant demand for efficient hardware accelerators capable of delivering high computational performance under strict power and resource constraints. Conventional neural network accelerators rely heavily on multiplication-intensive operations, large memory bandwidth, and analog-todigital (ADC) and digital-to-analog (DAC) conversion circuits, resulting in increased power consumption, silicon area, and processing latency. This paper presents a novel ADC/DAC-free neural network accelerator based on the Walsh– Hadamard Transform (WHT) and bitplane processing techniques for lowpower edge intelligence applications. The proposed architecture replaces conventional multiply-accumulate operations with addition and subtraction by exploiting the binary orthogonal properties of the Walsh–Hadamard matrix. A Block Walsh–Hadamard Transform (BWHT) compute core is developed to perform frequency-domain neural computation using fixed transform coefficients, thereby eliminating the need for trainable weight multiplications. To achieve high-precision processing without analog conversion circuits, multibit input data is decomposed into individual bitplanes and processed sequentially from the most significant bit to the least significant bit. The architecture further incorporates comparatorbased output generation, softthresholding for sparsity enhancement, and an early termination mechanism that dynamically halts unnecessary computations to reduce energy consumption and latency. The complete system is modeled and implemented using Verilog HDL and is optimized for FPGA realization. Experimental analysis demonstrates that the proposed accelerator significantly reduces computational complexity, memory overhead, power consumption, and hardware resource utilization while maintaining reliable neural computation. The elimination of multipliers, ADCs, and DACs, combined with frequency-domain processing and bit-plane computation, makes the proposed archi-tecture an efficient and scalable solution for next-generation edge AI systems, embedded intelligence platforms, and realtime machine learning applications.