A THREE-STAGE AMPLIFIER FOR POWERING BIG CAPACITIVE LOADS USING BUFFERED ASYMMETRIC DUAL PATH WITH CASCODE MILLER COMPENSATION

Abstract

This paper presents a new frequency compensation approach for threestage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gainbandwidth (GBW) product and 42.3◦ phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.