DESIGN AND IMPLEMENTATION OF VLSI USING BRENT KUNG ADDER IN THREE OPERAND BINARY ADDER

Abstract

Three operand adders are important arithmetic circuits used in modern VLSI systems, digital signal processing, and cryptographic applications. The speed and efficiency of arithmetic operations greatly affect the overall performance of digital systems. Conventional adder architectures suffer from high propagation delay, increased power consumption, and larger hardware complexity. This project presents the design and implementation of a high-speed and low-power three operand binary adder using parallel prefix architecture. The proposed adder uses four-stage structures including bit addition logic, base logic, propagategenerate logic, and sum logic to improve computational efficiency. Han-Carlson and parallel prefix techniques are incorporated to reduce critical path delay and optimize area utilization. The design is modeled using Verilog HDL and implemented using Xilinx ISE tools. Performance parameters such as delay, power consumption, and area are analyzed and compared with conventional adder architectures. Simulation results show that the proposed adder achieves better speed and lower power dissipation. The architecture is suitable for DSP systems, arithmetic processors, communication systems, and VLSI applications requiring high-speed computations.