VLSI Design and Implementation of a Polyphase Wavelet Filter for Power Quality Indices

Authors

  • K.Rama Chandrika1, Shaik Jaffar2 Author

DOI:

https://doi.org/10.62643/

Abstract

Power quality (PQ) has emerged as one of the most critical concerns in modern electrical engineering, driven by the rapid proliferation of power electronic devices, non-linear loads, and distributed energy resources. Issues such as voltage sags, swells, harmonic distortion, transients, flicker, and inter-harmonics can disrupt industrial processes, damage sensitive equipment, and result in significant financial losses. Therefore, accurate, real-time monitoring and analysis of power quality indices are of paramount importance for maintaining grid stability and reliability. The proposed system employs the Discrete Wavelet Packet Transform (DWPT) implemented using a polyphase network, which significantly reduces computational complexity and memory requirements while preserving the accuracy of wavelet decomposition. Unlike conventional DWPT implementations that provide only wavelet coefficients, the proposed design further integrates an on-chip Root Mean Square (RMS) calculation module, enabling direct computation of power quality indices without external postprocessing. The system was designed using MATLAB Simulink with the Xilinx Vitis Model Composer toolbox, enabling seamless translation of the algorithmic model into synthesizable hardware description language. The design targets the Xilinx Artix-7 AC701 FPGA evaluation board and was synthesized and implemented using the Vivado Design Suite. Filter coefficients derived from the db20 Daubechies wavelet family are quantized in an 18-bit fixed-point format with 12 fractional bits, balancing precision and hardware resource usage. Post-implementation results demonstrate that the design achieves a look-up table utilization of 21%, flip- flop utilization of 11%, and Digital Signal Processing block utilization of 60%, with a total power consumption of approximately 0.604 W. The design meets all timing constraints, with a worst negative slack (WNS) of 2.736 ns. Hardware co-simulation with both synthetic and real-world power quality disturbance signals confirms the accuracy and robustness of the implementation

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Published

27-05-2026

How to Cite

VLSI Design and Implementation of a Polyphase Wavelet Filter for Power Quality Indices. (2026). International Journal of Engineering Research and Science & Technology, 22(2(2), 594-600. https://doi.org/10.62643/