Design and Implementation of a High-Speed 64-Bit Carry Look-Ahead Decimal Adder (CLDA) using Verilog HDL in Xilinx Vivado

Abstract

The exponential scaling of CMOS transistor feature sizes in accordance with Moore's Law has enabled unprecedented levels of integration density, but has simultaneously introduced a new set of challenges for digital circuit designers. In deep submicron technologies (feature sizes below 130 nm), leakage power dissipation has emerged as a critical concern, approaching or even exceeding dynamic power in certain design scenarios. The traditional primary focus on area and performance optimization must now be augmented with rigorous power analysis and management strategies. This thesis presents a comprehensive comparative analysis of multiple adder and multiplier architectures, implemented at the physical level across four CMOS technology nodes: 45 nm, 90 nm, 180 nm, and 250 nm. The adder architectures investigated include the Ripple Carry Adder (RPL), Ripple Carry Select Adder (RPCS), Parallel Prefix Adder (PPARH), Conditional Sum Adder (CSM), Carry Look-Ahead Adder (CLA), and Brent-Kung Adder (BK). The multiplier architectures investigated include the Wallace Tree Multiplier (WALL), Booth-recoded Wallace Tree Multiplier (PPARCH), Non-Booth/Booth Hybrid Multiplier (NBW), and Carry-Save Array Multiplier (CSA). All architectures are implemented using synthesizable, technology-independent Verilog HDL instantiations from the Synopsys Design Ware Building Block IP. The synthesis is performed using Synopsys Design Compiler, and physical implementation (place and route) is carried out using Cadence SoC Encounter. Both unpipelined and two-stage pipelined versions are evaluated for bit widths of 16, 32, 64, and 128 bits (adders) and 16, 32, and 64 bits (multipliers). Performance metrics including dynamic power, leakage power, critical path delay, area, and gate count are extracted from post-layout simulation results. The analysis reveals that in deep submicron technologies, pipelining — contrary to its theoretical promise — does not always reduce power dissipation due to the significant overhead of pipeline registers. Among adder architectures, the Carry Look-Ahead (CLA) and Parallel Prefix (PPARCH) implementations consistently offer the best power delay-area trade-off. Among multiplier architectures, the Wallace Tree (WALL) and Parallel Prefix Booth Wallace (PPARCH) implementations deliver optimal results across all metrics.