Design and Optimization of a Hybrid PTL-TGL 4:1 Multiplexer Using MTCMOS Power Gating for Ultra Low-Power VLSI Applications

Abstract

Power dissipation and leakage currents have become critical challenges in deep-submicron VLSI design, particularly for portable and battery-operated systems. This work presents the design and optimization of a hybrid Pass Transistor Logic–Transmission Gate Logic (PTL–TGL) based 4:1 multiplexer integrated with a Multi-Threshold CMOS (MTCMOS) power-gating technique to achieve enhanced energy efficiency. The proposed hybrid logic architecture employs PTL to reduce transistor count and propagation delay, while TGL is utilized to ensure full voltage swing and improved signal integrity. To further suppress standby leakage power, a high-threshold sleep transistor is incorporated using the MTCMOS approach, effectively disconnecting the logic block from the power supply during idle states. The design is implemented and simulated using Tanner EDA tools in 90 nm CMOS technology. Simulation results demonstrate significant leakage power reduction with negligible delay overhead compared to conventional multiplexer designs. Owing to its favorable power–performance trade-off, the proposed architecture is well suited for modern low power and high-speed VLSI applications.