Design and Implementation of BIST Architecture For Low Power VLSI Applications Using Verilog

Abstract

With rapid growth of deep submicron technologies, testing of VLSI circuits has become increasingly complex, costly, and powerintensive. This paper presents the design and implementation of a Built-In Self-Test (BIST) architecture optimized for low-power VLSI applications, where the Circuit Under Test (CUT) is realized as an N×N multiplier. Multipliers are fundamental components in digital signal processing and arithmetic units, making their efficient testing critical for overall system reliability. The proposed BIST architecture integrates a low-power Test Pattern Generator (TPG), typically based on a Linear Feedback Shift Register (LFSR), and an Output Response Analyzer (ORA) using signature analysis techniques such as Multiple Input Signature Register (MISR). To address power concerns during testing, techniques such as clock gating, optimized switching activity, and reduced test vector transitions are incorporated. The N×N multiplier CUT is designed using an efficient architecture to minimize area and delay while maintaining compatibility with the BIST framework. Simulation results demonstrate that the proposed BIST approach achieves high fault coverage with significantly reduced power consumption compared to conventional external testing methods. Additionally, the design ensures minimal area overhead and maintains performance integrity of the multiplier. This work highlights an effective solution for integrating low-power self-test capabilities in modern VLSI systems, making it suitable for portable and high performance applications.