A Low-Area and Time-Efficient Hardware Architecture for Secure Comb Scalar Multiplication Using Recoding

Abstract

Elliptic Curve Cryptography (ECC) is widely used for secure communications, but hardware implementations often face a tradeoff between area, speed, and side-channel resistance. This paper proposes a novel low-area, time-efficient hardware architecture for secure comb-based scalar multiplication using advanced recoding techniques. The proposed system introduces three key innovations: 1. Adaptive Comb Recoding (ACR): A dynamic recoding strategy that optimizes the window size and precomputation table based on the input scalar, reducing both the number of point additions and memory footprint. 2. Hybrid Modular Arithmetic Unit (HMAU): Combines interleaved modular multiplication and a low-latency modular inverse algorithm to accelerate point operations while minimizing hardware resources. 3. Dual Randomization Security Layer (DRSL): Integrates Z-coordinate randomization and point blinding to resist simple and differential power analysis (SPA/DPA) without introducing performance overhead. The architecture is fully pipelined and designed for FPGA and ASIC platforms, achieving a significant reduction in area-time product (ATP) while maintaining high security. Simulation and synthesis results for a 256-bit prime field demonstrate up to 30% reduction in hardware slices and 25% lower latency compared to existing comb scalar multiplication architectures. The proposed design is suitable for resource-constrained embedded systems requiring secure an efficient ECC operations.